1. Field of the Invention
The present invention relates to an apparatus which inputs digital signals of two or more systems, performs switching processing and outputs the processed signals, particularly to the apparatus suitable for the input and output of digital signals to which status information formed of a block including a plurality of frames is added.
2. Description of the Related Art
As a kind of audio apparatus for broadcasting service, there is a switching apparatus called a digital audio router. The digital audio router is a switching apparatus that inputs digital audio signals of two or more systems (digital audio signals from a microphone, a video camera including microphone, and the like), and which outputs the digital audio signals respectively by switching apparatuses (VTR, Audio mixer, and the like).
The digital audio router may require the following two basic performances:
(1) an amount of processing delay in the apparatus is as small as possible; and
(2) an output signal after switching conforms to standards.
In order to satisfy those requirements, for example, Japanese Unexamined Utility Model (Registration) Application Publication No. H4-69938 discloses a digital audio router in which switching processing is performed on each frame after matching phases of input digital-audio signals to be switched.
FIG. 1 is a block diagram showing an example of a configuration of a digital audio router of the related art (the example including two input/output systems for the convenience of simplified explanation). Further, FIGS. 2A to 2G show an example of a timing chart when the digital audio router shown in FIG. 1 performs switching operation. Here, the digital audio router for AES/EBU signals frequently used in broadcasting service is shown in FIG. 1. Before explaining the digital audio router, an AES/EBU format is described using FIG. 3. The AES/EBU signal includes 192 frames from frame 0 to frame 191 constituting one block. One frame includes subframe1 and subframe2.
Each of the subframes includes 32 bits in total, specifically, four bits of preamble, four bits of auxiliary data or audio data, twenty bits of audio data, one bit of validity bit V, one bit of user bit U, one bit of channel status bit C, and one bit of parity bit P. The preambles of the subframe1 and subframe2 of the frame 0 are Z and Y respectively, and the preambles of subframe1 and subframe2 of frames 1 to 191 are X and Y respectively.
The channel status bit C of each subframe represents status information (information on frequency, number of bits of audio data, channel mode or the like) on the audio channel transferred using the subframe, and the status information as a whole is formed of one block including 192 bits (frames 0 to 191).
Returning to description on FIG. 1, the AES/EBU signals AESI1 and AESI2 of two systems (in general, signals phases of which are not matched as shown in FIGS. 2B and 2C) which are input to the digital audio router, are demodulated by decoders 51(1), 51(2) respectively to NRZ (Non Return to Zero) signals, which are written to FIFO memories 52(1), 52(2) for phase correction.
A CPU circuit/apparatus internal timing signal generating circuit 53 supplies a timing signal (word clock shown in FIG. 2A) generated in the digital audio router to the FIFO memories 52(1), 51(2) respectively. Upon receiving the timing signal, the NRZ signals NRZ1 and NRZ2 are read from the FIFO memories 52(1), 51(2) respectively in sync with a frame phase in the digital audio router (hereinafter called an internal frame phase), and are supplied to a selector 54. Thus, as is shown in FIGS. 2D and 2E, the NRZ signals NRZ1 and NRZ2 having the matched frame phases are input to the selector 54.
The selector 54 is a matrix switch of two inputs and two outputs, for example. The CPU circuit/apparatus internal timing signal generating circuit 53 supplies a switching signal to the selector 54 at a boundary portion between frames in the internal frame phase (as shown in FIG. 2F). Upon receiving the switching signal, the NRZ signals of two systems, to which switching processing is performed, are supplied to encoders 55(1), 55(2) from the selector 54.
Upon receiving the timing signal from the CPU circuit/apparatus internal timing signal generating circuit 53, the encoders 55(1), 55(2) modulate the NRZ signals to the AES/EBU signals AESO1, AESO2 respectively, to be output from the digital audio router. FIG. 2G shows a condition in which the output AES/EBU signal AESO1 is switched to the frame 4 of the input AES/EBU signal AESI1, from the frame 1 of the input AES/EBU signal AESI2.